The present invention in general relates to a semiconductor device and to a technique for the manufacture thereof, and, more particularly, the invention relates to a semiconductor device having a high breakdown voltage field effect transistor and to the manufacture thereof.
In a semiconductor device, a trench type isolation structure, called a “STI (Shallow Trench Isolation) or SGI (Shallow Groove Isolation)”, which is advantageous in that it tends to improve the degree of device integration, such as the ability to reduce the isolation width, etc., has recently been adopted as a device isolation structure. However, when a channel region of a low breakdown voltage MIS•FET, which is small in device size and low in applied voltage, is defined by a trench type isolation portion, an extraordinary kink effect is likely to occur in addition to a normal turn-on waveform. The kink effect is a phenomenon, in which when the dependence of the drain current on the drain voltage is measured, the drain current changes into an irregular bumped shape from a given voltage value, so that a stepwise waveform is generated. It is known that the major cause of the occurrence of the kink effect in the low breakdown voltage MIS•FET results from the fact that mechanical stress developed from the trench type isolation portion concentrates on each shoulder portion formed by a main surface of a semiconductor substrate and each side surface of the trench type isolation portion, and, hence, the grating constant of silicon at the shoulder portion changes, so that the mobility of carriers at the shoulder portion partly rises.
Thus, the cause of the occurrence of the kink effect in a low breakdown voltage MIS•FET results from the fact that the shape of each shoulder portion of the semiconductor substrate at each sidewall of the isolation portion is steep. Therefore, a rounding of the shoulder portion has become the main countermeasure against the kink effect.
As kink countermeasures other than the above, in the case of a low breakdown voltage MIS•FET, there is a technique wherein a high concentration impurity region of the same conduction type as a well is provided in a boundary portion between one of the trench type isolation portions and the semiconductor substrate. This technique has been disclosed in, for example, a patent document 1 (Japanese Unexamined Patent Publication No. Hei 9 (1997)-237829).
As another example, a patent document 2 (Japanese Unexamined Patent Publication No. 2001-144189) has disclosed a technique wherein, in a low breakdown voltage MOSFET comparted or laid out by a trench device isolation region, a central portion of a channel region thereof is configured as a p− type channel region that is low in threshold voltage, and both end portions in the neighborhood of the boundary between the channel region and the trench device isolation region are respectively configured as p+ type channel regions that are high in threshold voltage.
As a further, a patent document 3 (Japanese Unexamined Patent Publication No. Hei 10 (1998)-65153) has disclosed a technique in which an impurity layer that is higher in concentration than a channel region is provided at an outer peripheral portion of an active region defined by a trench type device isolation film having the same conduction type as the channel region so as to be shallower than a source/drain junction of a low breakdown voltage MIS•FET.
As a still further, a patent document 4 (Japanese Unexamined Patent Publication No. 2001-160623) has disclosed a technique wherein a low breakdown voltage MOSFET is formed in an active region defined by a device isolation film formed by a trench device isolation method, and channel edges of an active region below a gate electrode of the MOSFET are placed outside a region for injecting high concentration impurity ions for forming a source/drain region, to thereby turn the channel edges aside from an operation section for the purpose of preventing a kink effect.
As further methods of taking countermeasures against the kink effect, there have been proposed, for example, a method of ion-implanting nitrogen in each edge portion with respect to a semiconductor substrate that contacts a trench type isolation portion in an n channel type MOS•FET to form an SiN region, thereby preventing a reduction in the concentration of boron at the edge portion and reducing the leakage current caused by the kink effect, a method of thickening an oxide film in the neighborhood of each of trench type isolation portions to thereby reduce the kink effect, etc.